Capacitance sensing systems can utilize a mutual capacitance between transmit electrodes and receive electrodes to detect the proximity of an object (e.g., a finger). By application of an excitation signal, a charge (current) can be generated on a receive electrode that varies according to the mutual capacitance between the electrodes. Such a mutual capacitance can vary according to the proximity of an object. Such systems can be conceptualized as being “charge transfer” systems.
Some conventional touch screen sensing systems can utilize charge transferring methods. In these conventional systems, charge generated by a periodic excitation signal can be collected by an active integrator circuit over several excitation cycles. Such charge collection can be combined with demodulation to obtain a synchronous rectification of an incoming signal. Such conventional approaches can include a baseline compensation to prevent the integrator circuit from becoming saturated by non-informative capacitance. (Non-informative capacitance does not vary according to an object, i.e., touch)). Usually, non-informative capacitance can be 90% of the sensed capacitance (i.e., variation caused by a touch is usually 10% of the sensor capacitance).
Achieving a desired sensitivity in a charge transfer system can require that multiple sensing cycles (i.e., transitions of the excitation signal) be collected by the active integrator. Unfortunately, the noise immunity of such systems typically decreases in proportion to the number of sensing cycles. Consequently, the dynamic range of such conventional systems could be limited. Further, noise spikes in such conventional systems can result in integrators being driven into saturation, losing any measurement information.
One conventional approach to addressing the limitations of the above conventional charge transfer systems can be to deliver the results of a conversion after every excitation edge (i.e., transition of the excitation signal). Demodulation, integration, and analog to digital conversion can enable the generation of a digital value representing the capacitance. Satisfactory resolution in such conventional systems can rely on accumulation of the digital values having noise close to one least significant bit (LSB). Conventional approaches can utilize advanced filtration techniques during integration phase to minimize the external noise impact at the end of conversion.
A drawback to the above-noted conventional system can be that increases in the resolution of the sensing channel are proportional to the square-root of the accumulated conversions numbers. Thus, such a conventional system can require a relatively high-resolution analog-to-digital converter (ADC) that operates at a relatively low frequency and with a limited integration time. For example, integration of the convertor samples during 100 us, when the excitation signal frequency is 100 kHz, can correspond to an ADC resolution increasing by sqrt(20)=4.5 times (2 bits). Further, the digital accumulation of conversion results can require an ADC with very small differential nonlinearity (DNL) because the DNL is systematic for all the conversions result, and is not reduced by averaging values.
A second conventional approach to addressing the limitations of basic charge transfer systems can be to employ a “charge balancing” method. In a charge balancing method, an integrated input signal initially charges an integrating capacitor. The capacitance is then discharged by a reference current. Once the capacitor is returned to its initial state (i.e., it is balanced) the reference current is terminated. A charge balancing system is thus understood to be similar to a relaxation circuit. In some charge balancing systems, integration and charge balancing can occur at the same time. The time it takes to achieve such charge balancing can be converted to a digital value. For example, the number of reference clock pulses that occur over the charge balancing operation can be count value. This count value will vary according to the sensed capacitance. Charge balancing systems can have very good linearity as compared to basic charge transfer systems.
A drawback to a conventional charge balancing systems can be the sensitivity of a sense circuit (channel) to the incomplete recharging of the integrating capacitor, the possibility of the channel being synchronized by external noise, as well as the channel being susceptible to such noise.
FIG. 13 shows a conventional charge transfer system 1300 in a functional schematic diagram. Conventional system 1300 can include an excitation source Vex 1301 that drives a sensor network 1303 with a buffer 1305. In response to the excitation signal from source 1301, a sensor of sensor network 1303 can form an output current Im. Current Im corresponds to charge transferred through the sensor during a half-period of the excitation signal, and can represent a sensed capacitance (Cm). The current Im can be amplified by an input stage 1305 with gain k, and applied to a demodulator unit (DM) 1307. The DM 1307 is depicted functionally as a multiplier. Generally, the DM 1307 multiplies the incoming signal (Im) by the excitation signal to obtain a rectified output and obtain better noise immunity, especially in the presence of low frequency noise. In applying the demodulating signal to DM 1307, sometimes a phase shifter 1309 is included to minimize the impact of delay through the sensor network 1303.
The rectified signal output from the DM 1307 is collected in a low-pass filter (LPF) 1311 to generate an output signal (Ux) that is proportional to the transferred charge (Im) (which in turn is proportional to the sensed capacitance, Cm). Usually, an integrator is used in role of the LPF 1311. The LPF 1311 output is digitized by an ADC 1313, and collected in a digital low-pass filter (DLPF) 1315.
The architecture of FIG. 13 can be considered a “charge accumulation” architecture, as charge is accumulated at the LPF 1311 that is proportional to a sensed capacitance (Cm). In the conventional charge accumulation system 1300, the sensor excitation is periodic. The quantity of excitation charges that are collected in the LPF 1311 (and after that in the DLPF 1315) define the behavior of the system under a noise influence. The number of excitation periods accumulated and the excitation frequency can define the integration time.
The ADC conversion (ADC 1312) can take various forms. One ADC method can involve direct conversion. An incoming analog signal is compared to a quantized reference value. Another method can transform the integrated value to some other form. For example, a charge balancing type procedure can be used. In a charge balancing procedure, an initial charge corresponding to the integrated value can be balanced by application of reference current. The amount of time needed to balance out the value can then be digitized (i.e., by a counter, or the like).
FIG. 14A shows a conventional charge balancing system 1400 in a functional schematic diagram. A charge balancing system 1400 can include items like those of FIG. 13, and such like items are referred to by the same reference character but with the leading digits being “14” instead of “13”. Unlike FIG. 13, THE conventional system 1400 of FIG. 14 shows an integrator 1417, comparator 1419, and current source 1421, which can apply a current (represented by adder 1423) to the input signal at the input of the integrator 1423. A charge balancing system 1400 is understood to switch between opposite states after each charge balancing operation. Such system can be understood to perform input charge accumulation (integration) and charge balancing with a reference source at the same time.
It is noted that while a particular DM unit is not included in system 1400, demodulation can occur “virtually”, by operation of inverting current source, which can alternate the direction (sign) of a reference current source (e.g., charge balancing current Iref) synchronous with changes in the excitation signal.
The noise response of the conventional system 1400 will now be described. In general there can be two kinds of noise sources: internal and external. Internal noise can arise from the self-noise of active components, from charge transferred from switching circuit via parasitic capacitance, and from noise arising from power supplies. In FIG. 14A, such internal noise sources are reduced to an equivalent noise source Enc 1425 applied on at the input of comparator 1419 via a summing operation. External noise can penetrate into the measuring circuits via parasitic capacitance with sensors cells. Further, liquid crystal display (LCD) noise (if the system is utilized with a touchscreen) and charger noise are representative instances of external noise. In FIG. 14A, external noise sources are reduced to an equivalent source Ene connected to a sensors node via capacitor Cf within sensor network 1403.
The frequency response of the channel at the comparator input can be given as:Gconv(f)=Gf(f)·Gint(f)where Gf(f) is the transfer function of the noise source chain; Gint(f) is the integrator transfer function.
In a first approximation, Gf(f) and Gint(f) can be conceptualized as a high-pass and low-pass filters, respectively. In such a case, the frequency response of the system (i.e., channel) 1400 at the input of the comparator 1419 can be represented as a constant value:
                          Gf        ⁡                  (          f          )                            ≡          α      ·      f        ;                                      Gint          ⁡                      (            f            )                                      ≡              β        ·                  1          f                      ;    →                                    Gconv          ⁡                      (            f            )                                      ≅              constant        .            In other words the form of the noise spectrum at the sensing source and at the comparator input can be the same. As such, it is possible to analyze noise effects by moving all such noise sources to input of the comparator 1419.
FIG. 14B are timing diagrams showing errors that can result from noise in a system like that of FIG. 14A. A conversion operation (i.e., capacitance sensing operation) can begin with each transition of an excitation signal TX (points A and A′). Since the excitation signal acts on the integrator via differential gain, the integrator output voltage (Uint) changes fast from a reference voltage (Uref) up to a maximum value. A signal “Gate” connects a reference current (i.e., charge balancing) source to the integrator simultaneously. Thus, following the initial rise in value, Uint will start to discharge. Such a discharge stops when an integrator output voltage equals the reference voltage (Uref). Such stopping (i.e., charge balance) is marked as D and D′ in FIG. 14B.
FIG. 14B shows the influence of external noise sources (Enc) and internal noise sources (Ene). Noise is shown only at the end of a charge balancing operation. It is understood that such noise can be present all along the waveforms and is just shown as the Uint approaches Uref, for illustration.
FIG. 14B shows how similar conversion operations occur under the different noise sources. As shown, effects of noise can result in a shortening of the charge balancing time (shown as point B for noise Enc, and point C for noise Ene). In other words, the normal distribution of noise would change a value of distributions to be skewed to one side (i.e., shorter charge balancing time, or smaller count values).
It is noted that the type of distribution does not change if a slew rate of noise in the comparator input is less than the integrator output voltage slew rate at the end of a discharge operation. In this way, integrator discharge speed and noises spectrum may significantly impact converter behavior in a conventional charge balancing system.
FIG. 14C is a timing diagram showing how a conventional charge balancing system can have increasing error in subsequent conversions. In particular, there can be a doubling in error from the previous conversion to the following conversion. In response to noise, the discharge process can stop too early (point B). At this point, the integrator output voltage (Uint) is different than reference voltage (Uref). Therefore, the following conversion begins from this (non reference) level and the error from first conversion (corresponding to point A to B) is carried into the second conversion, which, due to noise, can cut short the balancing time even more (point A′ to B′). Thus, an error of a second conversion (−Δns′) can be greater than that of a first conversion (−Δns).
FIG. 15 shows a conventional relaxation converter based system 1500 with a charge-charge balancing technique. System 1500 can include two operational amplifiers (op amps) OA0 and OA1. OA0 in combination with an integrating capacitor Cint can be used as an active integrator, with the capacitor Cint in a feedback loop. OA1 can serve as a comparator 1519 to indicate the moment when charge balancing occurs in the integrating capacitor Cint. Non-inverted inputs of OA0 and OA1 can be connected to a reference voltage Uref, which can be at a point close to a middle of the supply voltage. A signal from a sensor (Im) is applied directly to an input of the integrator.
A current digital-to-analog convertor (I-DAC) 1521 generates a balancing current (Iref) that is applied to the integrator input with switch 1529, which is controlled by signal Gate. Digital code Ni establishes a magnitude of the balancing current (Iref). Balancing begins with excitation edge (rising or falling edge of Tx) and stops when the comparator determines that the integrator output voltage (Uint) has crossing the reference level (Uref). The next edge of Tx is a start point for the following conversion.
Convertor control logic 1527 generates signals that control the excitation source (Tx) and a signal “Polarity”, which switches the direction flow of the balancing current. These two signals (Tx and Polarity) are strongly correlated. In the case of a large noise event that changes the integrator output voltage to a polarity opposite to that of the excitation signal, the balancing current will be of the wrong polarity, reinforcing the excitation signal and driving the integrator into saturation. Control logic 1527 can use the comparator output to define the balancing current polarity to prevent integrator saturation in a large noise environment. In particular, when a balancing current is of the wrong polarity, the conversion result is represented as negative number, indicating it is an invalid measure.
A convertor resolution is defined as product of balancing time and (a counting) clock frequency. The clock is used to measure the balancing time by counting number of the clock pulses occurring over the balancing time period. The balancing time is limited by the excitation signal half-period duration. This means that it can be difficult to obtain a high resolution of the convertor when using a high frequency excitation signal.
The result of conversion of one excitation edge can be given by:
      Nx    =                            Uex          ·          Cx                Ibal            ·      Fclk        ;Where Uex is the excitation voltage; Cx is the sensor capacitance; Ibal is the balancing current; and Fclk is the clock frequency. It should be noted that the integrating capacitor value is absent in the convertor equation above. This capacitance defines the integrator output voltage swing only. The structures based on the direct conversion of integrator output (noted above) are sensitive to the integrating capacitor value.
A conventional relaxation type charge balancing system like that of FIG. 15 can have the following advantages: insensitivity to integrating capacitor value; overload immunity; a simple structure; and cycle by cycle processing possibilities. Drawbacks to such a system can be: large quantization noise; response and degradation are worse as noise levels grow; such systems need a bi-directional reference current source; external noise can provoke synchronization or resonance; and many parameters define ringing frequency.